Frequency dividers, or prescalers, may be used for both analogue and digital applications and are essential building blocks in frequency synthesizers. A frequency divider is an electronic circuit that is adapted to receive an input clock signal with a reference frequency, fref, and generate an output clock signal with a frequency, fout, that is a fraction of the reference frequency, fref, of the input clock signal:
      f    out    =                    f        ref            n        .  Most frequency dividers are integer dividers. Integer frequency dividers have a frequency division ratio of n=2, 3, 4, . . . , N. An example of an integer frequency divider circuit is the divide-by-2 frequency divider circuit shown in FIG. 1. However, it is particularly interesting to realize non-integer frequency dividers. A non-integer frequency divider may also be referred to as a fractional frequency divider. This is because non-integer frequency dividers increase the flexibility in the choice of which reference frequency the input clock signal must have in order to generate a given output frequency. A non-integer digital frequency divider circuit comprising an arrangement of multiple master-slave flip-flops adapted to achieve frequency division ratios of fourths, that is, n=1.25, 1.5, 1.75, . . . ,
  N  4is disclosed in European patent application EP 1 562 294 A1. However, a disadvantage with this non-integer digital frequency divider circuit is that it is not fast enough for high-speed applications and may create spurious frequencies (or spurs) in the output due to its inherent non-symmetric configuration.
The speed of a circuit can be calculated by checking its critical path. The critical path of a circuit can be described as the longest path through asynchronous logic between sequential storage elements sharing a common clock signal, e.g. bi-stable memory devices such as flip-flops and/or latches. Since the speed of any circuit is generally limited by the longest delay along its paths, the maximum allowed delay along the critical path of a circuit is a useful metric of the performance of the circuit. For the non-integer digital frequency divider circuit disclosed in European patent application EP 1 562 294 A1, a critical path can be identified as the path from the output of the data latch L4 through the data latch L8 and the NAND-gates 6 and 7. This introduces a maximum allowed delay for the digital frequency divider circuit of a ¼ of the period of the input clock signal. This maximum allowed delay along with the non-symmetric digital circuit configuration limits the speed and performance of the non-integer digital frequency divider circuit.